Accessing DDR Subsystem Through Native Interface

The DDR subsystem can be used to access SDRAMs directly, as shown in the following figure.

Figure 1. DDR Subsystem Accessed Through Native Interface

User logic is connected directly to the DDR subsystem using the native interface.

After successful DDR initialization, the native interface master initiates reads from or writes to the DDR memory. The following steps describe how to create a design to access the DDR3 memory from the native interface master in the FPGA fabric:

  1. 1.Create a SmartDesign, and instantiate the DDR3 macro.
  2. 2.Configure the DDR3 subsystem as described in Implementation, or apply the preset configuration (if any), and select the native interface, as shown in the following figure.

    In this example, the design is created to access the DDR3 memory with a 16-bit data width through the native interface.

    Figure 2. Native Interface Selection
  3. 3.Instantiate the user native interface master logic in the SmartDesign canvas. Ensure that the native interface master logic accesses the DDR3 subsystem only after CTRLR_READY is high.
  4. 4.In the SmartDesign canvas, connect the blocks, as shown in the following figure.
    Figure 3. SmartDesign Connection—Native Interface
  5. 5.Follow steps 7–11 of Accessing DDR Subsystem Through AXI4 Interface to simulate the design and see the read and write transactions.