Simulating QDR Memory Controller

Libero SoC supports simulation for the QDR Subsystem, which includes a training sequence. For simulating this Subsystem, the QDR SRAM interface must be connected to the vendor-specific QDR memory simulation model in a testbench. Memory vendors (like Cypress Semiconductor) provide downloadable simulation models for memory devices. For more information on Simulations: Set-up and Running, see Functional Example.