- 1.The address and command groups must be
skew matched with respect to CK signals within ±100 ps.
- 2.The DQ, DM signals must be skew matched
with respect to DQS within ±25 ps.
- 3.The read DQ/DQS training adjusts the DQS signal to optimal sampling point based on the
board skew between DQ and DQS.
- 4.The write level training ensures that the tDQSS specification for memory is matched for
each of the DQ/DQS byte groups and offset the skew introduced due to fly-by
routing.
The characteristic impedance of 40 Ω–50 Ω must be used for single ended
signals and 90 Ω–100 Ω for differential signals.