DFI Initialization

In this step, the PHY de-asserts the DFI_INIT_COMPLETE signal (1’b0) to indicate that the PHY is not ready to accept DFI commands. After the RESET release, the PHY goes through the following PLL Lock and Clock Training sequence, which does not require any controller or user intervention.

  1. 1.Initializes the PLL and waits for the lock signal.
  2. 2.Switches SYS_CLK to PLL HSIO_CLK/4 clock.
  3. 3.Sets the IOA buffer Vref to 50%.
    Note: VREF is set either internally or externally by a pin at device power-up.
  4. 4.Aligns HSIO_CLK to SYS_CLK.
  5. 5.Aligns REF_CLK (CK0/CK0_N) to ADD/CMD bus.

This completes the DFI and IOD initialization. The Training IP asserts the DFI_INIT_COMPLETE signal (1) indicating the controller to start the DDR training procedure. The PHY is now ready to accept DFI commands.

Note: After dfi_init_complete assertion, the controller must keep DFI_RESET_N_P* / DFI_CKE_P* low for 200 μs, and then drive DFI_RESET_N_P* high. After that, the controller must wait for another 500 μs and assert DFI_CKE_P* high. This is required as per the JEDEC specification.