The QDR Subsystem macro (PolarFire QDR) located in the Libero IP catalog must be instantiated in SmartDesign to access the QDR memory from the FPGA fabric through the subsystem. The QDR Configurator shown in the following figure configures the QDR Subsystem.
Figure 1. QDR Configurator
The following fields are available for configuring the QDR Subsystem:
- Data rate: Allows you to set the data rate of QDR SRAM memory. The K/CQ Clock frequencies are calculated using data rate value (divide by 2). The FPGA logic (SYS_CLK) frequency is automatically populated (data rate/8).
- CCC PLL clock Multiplier: Allows you to set the QDR Subsystem PLL Clock multiplier. The PLL Reference Clock frequency must be K/CQ frequency / CCC PLL Clock multiplier.
- QDR data width: Allows you to set 9,18,36-bit data width.
- Address width: Allows you to set 18 to 21-bit address width.
- Burst size: Allows you to select burst size of 2 or 4.
- Simulation mode: PolarFire QDR Subsystem supports following
simulation modes:
- BFM: In this mode, the QDR subsystem skips the training sequence and asserts the TRAINING_COMPLETE signal. QDR memory model is not required for BFM simulation.
- RTL_Fast: In this mode, the QDR subsystem loads the training delays as per the selected configuration, skips the training sequence and asserts the TRAINING_COMPLETE signal. QDR memory model is required for RTL_Fast simulation.
- RTL_Full: In this mode, the QDR subsystem performs the training sequence and asserts the TRAINING_COMPLETE signal. TRAINING_COMPLETE is asserted within 10 ms. QDR memory model is required for RTL_FULL simulation.
- Additional pipelining levels: This option is used for static timing closure, if necessary. Enabling this option increases the read latency by 2 - 3 SCLK cycles.