Functional Description

The Fabric DDR subsystem translates the AXI/native interface requests into command sequences required by SDRAM devices. The DDR controller module then issues these commands to the PHY module, which sends and receives data to and from the DDR SDRAM.

The training logic manages DDR PHY interface (DFI) 3.1 requests between the I/O lane and the DDR controller. The PLL generates the clocks required by the DDR subsystem. For more information about the PLL, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide.