After Write Calibration, the DDR subsystem is ready for a normal operation. Typically, the controller asserts a signal like CTRLR_READY to let the host system know that the DDR subsystem is now ready for normal DDR operations.
This step describes a simple Burst Write operation along the DFI interface. This step describes how the controller must drive the DFI interface for a simple Burst Write operation and the associated timing parameters. There are two timing parameters associated with the WRITE Command, tphy_wrdata, and tphy_wrlat. Figure 1 shows how these timing parameters are used by the controller. The controller must be aware, must parameterize and hold constant all of the PHY related timing during operations. The controller must know the PHY protocol related timing defined in the DFI 3.1 specification. For more information on timing, see the DFI 3.1 sequence.
In the frequency ratio (4:1) system, the controller must follow the phase relationship and timing. The following examples for CWL = 7 & CWL = 8 where the controller must calculate the phase to drive WRDATA_EN, WRDATA, and WRDATA_MASK.
If CWL = 7 and DFI_WRDATA_EN {P3} are asserted in two DFI clocks (SYS_CLK) after issuing the Write command. DFI_WRDATA_EN {P0, P1, P2} are asserted in the third clock cycle. WRDATA & WRDATA_MASK are issued in the next phase after the issuing WRDATA_EN, as shown in the following figure.
If CWL = 8 and DFI_WRDATA_EN {P0, P1, P2, P3} are asserted in three DFI clocks (SYS_CLK) after issuing the Write command. WRDATA & WRDATA_MASK are issued in the next phase after issuance of WRDATA_EN, as shown in the following figure.
The following figures show simple burst write sequence for 16 and 32 bit interfaces.
