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AVR® DB Family

AVR128DB64 AVR128DB48 AVR128DB32 AVR128DB28

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42 Package Drawings
42.10 48-Pin VQFN Wettable Flanks

Introduction
AVR® DB Family Overview
Features
1 Block Diagram
2 Pinout
3 I/O Multiplexing and Considerations
4 Hardware Guidelines
5 Power Supply
6 Conventions
7 AVR® CPU
8 Memories
9 GPR - General Purpose Registers
10 Peripherals and Architecture
11 NVMCTRL - Nonvolatile Memory Controller
12 CLKCTRL - Clock Controller
13 SLPCTRL - Sleep Controller
14 RSTCTRL - Reset Controller
15 CPUINT - CPU Interrupt Controller
16 EVSYS - Event System
17 PORTMUX - Port Multiplexer
18 PORT - I/O Pin Configuration
19 MVIO - Multi-Voltage I/O
20 BOD - Brown-out Detector
21 VREF - Voltage Reference
22 WDT - Watchdog Timer
23 TCA - 16-bit Timer/Counter Type A
24 TCB - 16-Bit Timer/Counter Type B
25 TCD - 12-Bit Timer/Counter Type D
26 RTC - Real-Time Counter
27 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
28 SPI - Serial Peripheral Interface
29 TWI - Two-Wire Interface
30 CRCSCAN - Cyclic Redundancy Check Memory Scan
31 CCL - Configurable Custom Logic
32 AC - Analog Comparator
33 ADC - Analog-to-Digital Converter
34 DAC - Digital-to-Analog Converter
35 OPAMP - Analog Signal Conditioning
36 ZCD - Zero-Cross Detector
37 UPDI - Unified Program and Debug Interface
38 Instruction Set Summary
39 Electrical Characteristics
40 Characteristics Graphs
41 Ordering Information
42 Package Drawings
43 Data Sheet Revision History
Microchip Information

42.10 48-Pin VQFN Wettable Flanks

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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