25.14 Register Summary - Timer1
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x031B | Reserved | |||||||||
| 0x031C | TMR1 | 7:0 | TMR1[7:0] | |||||||
| 15:8 | TMR1[15:8] | |||||||||
| 0x031E | T1CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x031F | T1GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0320 | T1GATE | 7:0 | GSS[5:0] | |||||||
| 0x0321 | T1CLK | 7:0 | CS[4:0] | |||||||
0x0322 ... 0x0327 | Reserved | |||||||||
| 0x0328 | TMR3 | 7:0 | TMR3[7:0] | |||||||
| 15:8 | TMR3[15:8] | |||||||||
| 0x032A | T3CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x032B | T3GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x032C | T3GATE | 7:0 | GSS[5:0] | |||||||
| 0x032D | T3CLK | 7:0 | CS[4:0] | |||||||
0x032E ... 0x0333 | Reserved | |||||||||
| 0x0334 | TMR5 | 7:0 | TMR5[7:0] | |||||||
| 15:8 | TMR5[15:8] | |||||||||
| 0x0336 | T5CON | 7:0 | CKPS[1:0] | SYNC | RD16 | ON | ||||
| 0x0337 | T5GCON | 7:0 | GE | GPOL | GTM | GSPM | GGO/DONE | GVAL | ||
| 0x0338 | T5GATE | 7:0 | GSS[5:0] | |||||||
| 0x0339 | T5CLK | 7:0 | CS[4:0] | |||||||