29.5.4 Host Control A
| Name: | MCTRLA |
| Offset: | 0x03 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RIEN | WIEN | QCEN | TIMEOUT[1:0] | SMEN | ENABLE | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – RIEN Read Interrupt Enable
A TWI host read interrupt will only be generated if this bit and the Global
Interrupt Enable (I) bit in the Status (CPU.SREG) register are set to
‘1’.
Writing a ‘1’ to this bit enables the interrupt on the Read
Interrupt Flag (RIF) in the Host Status (TWIn.MSTATUS) register. The RIF flag is
set to ‘1’ when the host read interrupt occurs.
Bit 6 – WIEN Write Interrupt Enable
A TWI host write interrupt will only be generated if this bit and the Global
Interrupt Enable (I) bit in the Status (CPU.SREG) register are set to
‘1’.
Writing a ‘1’ to this bit enables the interrupt on the Write
Interrupt Flag (WIF) in the Host Status (TWIn.MSTATUS) register. The WIF flag is
set to ‘1’ when the host write interrupt occurs.
Bit 4 – QCEN Quick Command Enable
Writing a ‘1’ to this bit enables the Quick Command mode. If the
Quick Command mode is enabled and a client acknowledges the address, the
corresponding Read Interrupt Flag (RIF) or Write Interrupt Flag (WIF) will be
set depending on the value of the R/W bit.
The software must issue a Stop command by writing to the Command (MCMD) bit field in the Host Control B (TWIn.MCTRLB) register.
Bits 3:2 – TIMEOUT[1:0] Inactive Bus Time-Out
Setting this bit field to a non-zero value will enable the inactive bus time-out supervisor. If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the Idle state.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLED | Bus time-out disabled - I2C |
| 0x1 | 50US | 50 µs - SMBus (assume the baud rate is set to 100 kHz) |
| 0x2 | 100US | 100 µs (assume the baud rate is set to 100 kHz) |
| 0x3 | 200US | 200 µs (assume the baud rate is set to 100 kHz) |
Bit 1 – SMEN Smart Mode Enable
Writing a ‘1’ to this bit enables the Host Smart mode. When the
Smart mode is enabled, the existing value in the Acknowledge Action (ACKACT) bit
from the Host Control B (TWIn.MCTRLB) register is sent immediately after reading
the Host Data (TWIn.MDATA) register.
Bit 0 – ENABLE Enable TWI Host
Writing a ‘1’ to this bit enables the TWI as host.