31.4 Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | CTRLA | 7:0 | RUNSTDBY | ENABLE | ||||||
| 0x01 | SEQCTRL0 | 7:0 | SEQSEL0[3:0] | |||||||
| 0x02 | SEQCTRL1 | 7:0 | SEQSEL1[3:0] | |||||||
0x03 ... 0x04 | Reserved | |||||||||
| 0x05 | INTCTRL0 | 7:0 | INTMODE3[1:0] | INTMODE2[1:0] | INTMODE1[1:0] | INTMODE0[1:0] | ||||
0x06 | Reserved | |||||||||
| 0x07 | INTFLAGS | 7:0 | INT3 | INT2 | INT1 | INT0 | ||||
| 0x08 | LUT0CTRLA | 7:0 | EDGEDET | OUTEN | FILTSEL[1:0] | CLKSRC[2:0] | ENABLE | |||
| 0x09 | LUT0CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x0A | LUT0CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x0B | TRUTH0 | 7:0 | TRUTH0[7:0] | |||||||
| 0x0C | LUT1CTRLA | 7:0 | EDGEDET | OUTEN | FILTSEL[1:0] | CLKSRC[2:0] | ENABLE | |||
| 0x0D | LUT1CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x0E | LUT1CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x0F | TRUTH1 | 7:0 | TRUTH1[7:0] | |||||||
| 0x10 | LUT2CTRLA | 7:0 | EDGEDET | OUTEN | FILTSEL[1:0] | CLKSRC[2:0] | ENABLE | |||
| 0x11 | LUT2CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x12 | LUT2CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x13 | TRUTH2 | 7:0 | TRUTH2[7:0] | |||||||
| 0x14 | LUT3CTRLA | 7:0 | EDGEDET | OUTEN | FILTSEL[1:0] | CLKSRC[2:0] | ENABLE | |||
| 0x15 | LUT3CTRLB | 7:0 | INSEL1[3:0] | INSEL0[3:0] | ||||||
| 0x16 | LUT3CTRLC | 7:0 | INSEL2[3:0] | |||||||
| 0x17 | TRUTH3 | 7:0 | TRUTH3[7:0] | |||||||