Figure 39-110. Gain Error vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V)
Figure 39-111. Gain Error vs.
Sample Rate (ADC Single Ended Mode, VREFA =
VDD = 3.0V)
Figure 39-112. Offset Error
vs. VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V)
Figure 39-113. Offset Error
vs. Sample Rate (ADC Single Ended Mode, VREFA =
VVDD = 3.0V)
Figure 39-114. DNL vs. ADC
code (ADC Single Ended Mode @60 ksps, VDD =
3.0V)
Figure 39-115. INL vs. ADC
code (ADC Single Ended Mode @60 ksps, VDD =
3.0V)
Figure 39-116. DNL vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V, T = 125°C)
Figure 39-117. DNL vs. Sample
Rate (ADC Single Ended Mode, VREFA = VDD =
3.0V, T = 125°C)
Figure 39-118. INL vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V, T = 125°C)
Figure 39-119. INL vs. Sample
Rate (ADC Single Ended Mode, VREFA = VDD =
3.0V, T = 125°C)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
