26.13.2 Status
| Name: | STATUS |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMPBUSY | PERBUSY | CNTBUSY | CTRLABUSY | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – CMPBUSY Compare Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing
the Compare (RTC.CMP) register in the RTC clock domain.
Bit 2 – PERBUSY Period Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing
the Period (RTC.PER) register in the RTC clock domain.
Bit 1 – CNTBUSY Counter Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing
the Count (RTC.CNT) register in the RTC clock domain.
Bit 0 – CTRLABUSY Control A Synchronization Busy
This bit is ‘1’ when the RTC is busy synchronizing
the Control A (RTC.CTRLA) register in the RTC clock domain.