7.6.1 Configuration Change Protection
| Name: | CCP |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCP[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – CCP[7:0] Configuration Change Protection
Writing the correct signature to this bit field allows changing protected I/O registers or executing protected instructions within the following four CPU instructions executed.
All interrupts are ignored during these cycles. After completing these cycles, the interrupts will be handled automatically by the CPU. Any pending interrupts will be executed according to their level and priority.
When the protected I/O register signature is written, CCP[0] will read
‘1’ as long as the CCP feature is enabled.
When the protected self-programming signature is written, CCP[1] will read
‘1’ as long as the CCP feature is enabled.
CCP[7:2] will always read ‘0’.
| Value | Name | Description |
|---|---|---|
| 0x9D | SPM | Allow self-programming |
| 0xD8 | IOREG | Unlock protected I/O registers |