3.1 Operation

When using a static priority interrupt vector table, the lowest interrupt vector address has the highest priority. This means, when two or more interrupts are pending, the order of execution will be set by the interrupt vector address, in ascending order. See Figure 3-1 for a graphical representation.

While the CPU is executing an ISR, any new IRQs will be kept pending until the running routine is complete, and at that time the interrupt with the lowest vector address (highest priority) will be executed first.

Figure 3-1. Interrupt Priority Using Static Priority Scheme

In Static Priority Interrupt Scheme the CPUINT.LVL0PRI register defines the starting point for the highest priority interrupt, so it is possible to statically shift the priority in the vector table by writing the desired interrupt vector address to LVL0PRI. The default value of this register is 0x00, so after reset, the lowest address interrupt vector will have the highest priority.