4.1 Operation

When using the Round-Robin Priority Scheme, the interrupt controller will store the address of the latest acknowledged interrupt; in the event that more than one interrupt request is pending, the stored address will have the lowest priority when the next interrupt is due to be serviced. Consequently, the next higher interrupt vector address will be assigned the highest priority. See Figure 4-1 for a graphical representation of the scheme.

Figure 4-1. Interrupt Priority Using Round-Robin Interrupt Scheme

The Round-Robin Priority Scheme is enabled by writing '1' to the LVL0RR bit in the CPUINT.CTRLA register. The CPUINT.LVL0PRI register will contain the address of the last acknowledged interrupt. This becomes the lowest priority interrupt when the interrupt controller decides which interrupt to execute next.

By changing the value in CPUINT.LVL0PRI it is possible for the CPU to change which interrupts have the lowest and highest priority next. The default value of this register is 0x00, so after reset the lowest interrupt vector will have the highest priority.