6.1 Operation

There are specific vectors that have a hardwired NMI priority level, which cannot be changed. They must be enabled the same way as other interrupts. Refer to the Interrupt Vector Mapping of the device datasheet for available NMI sources.

By reading the LVL0EX and LVL1EX bits in the CPUINT.STATUS register, the application can check whether any level 0 or level 1 ISR has been interrupted by an NMI.