36.3.2.2 ZCD Logic Output
The STATE flag in the ZCDn.STATUS register indicates whether the
input signal is above or below the reference voltage, ZCPINV. By default, the
STATE flag is ‘1’ when the input signal is above the reference voltage and
‘0’ when the input signal is below the reference voltage. The polarity
of the STATE flag can be reversed by writing the INVERT bit to ‘1’ in the
ZCDn.CTRLA register. The INVERT bit will also affect ZCD interrupt polarity.