18.3.2.5 Virtual Ports
The Virtual PORT registers map the most frequently used regular PORT registers into the I/O
         Register space with single-cycle bit access. Access to the Virtual
            PORT registers has the same outcome as access to the regular registers but allows for
            memory-specific instructions, such as bit manipulation instructions, which cannot be
            used in the extended I/O Register space where the regular PORT registers reside.
         The following table shows the mapping between the
         PORT and VPORT registers.
| Regular PORT Register | Mapped to Virtual PORT Register | 
|---|---|
| PORTx.DIR | VPORTx.DIR | 
| PORTx.OUT | VPORTx.OUT | 
| PORTx.IN | VPORTx.IN | 
| PORTx.INTFLAGS | VPORTx.INTFLAGS | 
Note: Avoid accessing the mapped VPORT register using the single-cycle I/O instructions
         immediately after accessing the regular PORT register. This may cause a memory collision
         since the single-cycle I/O access to VPORT is faster than the regular PORT register access. 
