29.5.5 Host Control B
| Name: | MCTRLB |
| Offset: | 0x04 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLUSH | ACKACT | MCMD[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 3 – FLUSH Flush
This bit clears the internal state of the host and the bus states changes to Idle. The TWI will transmit invalid data if the Host Data (TWIn.MDATA) register is written before the Host Address (TWIn.MADDR) register. Writing to Host Address (TWIn.MADDR) and Host Data (TWIn.MDATA) after a Flush will cause a transaction to start as soon as hardware detects SCL bus free.
Writing a ‘1’ to this bit generates a strobe for one clock
cycle, disabling the host and then re-enabling the host. Writing a
‘0’ to this bit has no effect.
Bit 2 – ACKACT Acknowledge Action
The ACKACT(1) bit represents the behavior in
the Host mode under certain conditions defined by the bus state and the software
interaction. If the Smart Mode Enable (SMEN) bit in the Host Control A
(TWIn.MCTRLA) register is set to ‘1’, the acknowledge action is
performed when the Host Data (TWIn.MDATA) register is read. Otherwise a command
must be written to the Command (MCDM) bit field in the Host Control B
(TWIn.MCTRLB) register.
The acknowledge action is not performed when the Host Data (TWIn.MDATA) register is written since the host is sending data.
| Value | Name | Description |
|---|---|---|
| 0 | ACK | Send ACK |
| 1 | NACK | Send NACK |
Bits 1:0 – MCMD[1:0] Command
The MCMD(1) bit field is a strobe. This bit field
always reads as ‘0’.
Writing to this bit field triggers a host operation, as defined by the table below.
| MCMD[1:0] | Group Configuration | DIR | Description |
|---|---|---|---|
0x0 |
NOACT | X | Reserved |
0x1 |
REPSTART | X | Execute Acknowledge Action followed by repeated Start condition |
0x2 |
RECVTRANS | W |
Execute Acknowledge Action (no action) followed by a byte write operation(2) |
| R | Execute Acknowledge Action followed by a byte read operation | ||
0x3 |
STOP | X | Execute Acknowledge Action followed by issuing a Stop condition |
- The ACKACT bit and the MCMD bit field can be written simultaneously.
- For a host write operation, the TWI will wait for new data to be written to the Host Data (TWIn.MDATA) register.