3 Conclusion

In this white paper, the WCET results for a 32 x 32 matrix multiplication task in bare metal were analyzed by executing the task from ITIM, LIM, and DDR cached regions. In all three cases, the task execution time increased due to the latency factors which resulted in WCET. The effects of L2 cache refresh and flush functions were negligible when the tasks were executing from ITIM or LIM.

On U54_1, when the task was executing from ITIM with LIM as target memory for data and stack, the additional latency resulted mainly from the interrupt execution latency factor.

On U54_1, when the task was executing from LIM (code, data, and stack), the additional latency resulted mainly from the interrupt execution latency factor. In this case, when the task was executed multiple times, there was a deviation in the execution time mainly due to branch prediction trashing.

On U54_4, when the task was executing from DDR cached region (code, data, and stack), the additional latency and execution time deviation were higher when compared to the above two cases. This is due to the L2 cache refresh/flush and interrupt execution latency factors. However, the minimum execution time was achieved due to the presence of caches.

Based on the above results, the task executing from ITIM with LIM as target memory for data and stack gave more deterministic behavior.