1 Latency Factors

In PolarFire SoC devices, the following hardware and software factors affect the upper-bound of the software execution time.

• Memory region—placement of code, data, and stack segments affect the execution time of a task. Code placed in Instruction Tightly Integrated Memory (ITIM) executes faster than the code placed in DDR memory. Similarly, data placed in DDR memory (cached region) can be accessed faster than data in Loosely Integrated Memory (LIM).
• Cache configuration—LIM, scratchpad, and L2 cache.
• Interrupts—outside event can trigger an interrupt, which might not be in the user's control. In such events, the CPU core halts the execution of the current task and executes the interrupt handler. As a result, the execution time gets incremented.
• Total concurrent tasks in the system.
• Branch prediction and execution pipeline also increment the execution time.
• Toolchain settings (ISA, optimization settings) and Programming Style (Efficiency of the code).

For the WCET task used for this white paper, WCET is measured in terms of execution cycles using the hardware performance monitoring register. For more information about the hardware performance monitoring register, ITIM and LIM, and other MSS functional blocks, see PolarFire SoC MSS Technical Reference Manual.

The following section describes an example bare metal application used for white paper.