7.1 Core Descriptions

The table list all instructions that vary between the different cores and marks if it is included in the core. If the instruction is not a part of the table, then it is included in all cores.

Table 7-1. Core Description
Instructions	AVR	AVRe	AVRe+	AVRxm	AVRxt	AVRrc
ADIW	x	x	x	x	x
BREAK		x	x	x	x	x
CALL		x	x	x	x
DES				x
EICALL			x	x	x⁽¹⁾
EIJMP			x	x	x⁽¹⁾
ELPM			x	x	x
FMUL			x	x	x
FMULS			x	x	x
FMULSU			x	x	x
JMP		x	x	x	x
LAC				x
LAS				x
LAT				x
LDD	x	x	x	x	x
LPM	x	x	x	x	x
LPM Rd, Z		x	x	x	x
LPM Rd, Z+		x	x	x	x
MOVW		x	x	x	x
MUL			x	x	x
MULS			x	x	x
MULSU			x	x	x
SBIW	x	x	x	x	x
SPM		x	x	x	x
SPM Z+				x	x
STD	x	x	x	x	x
XCH				x

Note:

For devices with memory greater than 128 KB the EIJMP and EICALL instructions are valid.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.