PIC18-Q35 Family Summary
| Devices |
PIC18F26Q35 PIC18F46Q35 PIC18F56Q35 |
|---|---|
| Program Flash Memory | 64 KB |
| Data SRAM | 4 KB |
| Data EEPROM | 256B |
| Memory Access Partition (MAP) | Yes |
| Device Information Area (DIA) | Yes |
| Programming and Debugging Interface Disable (PDID) | Yes |
| Feature | PIC18F26Q35 | PIC18F46Q35 | PIC18F56Q35 |
|---|---|---|---|
| Pins | 28 | 40 | 48 |
| I/O Pins | 24 | 35 | 43 |
| Peripheral Pin Select (PPS) | Yes | Yes | Yes |
| Multi-Voltage I/O (MVIO) Pins | 4 (on VDDIO2) | 12 (on VDDIO2) | 12 (on VDDIO2) |
| High-Voltage Tolerant Pins | 4 | 12 | 12 |
| Signal Routing Port (8-Pin) | 1 | 1 | 1 |
| 8-Bit Timer with HLT (TMR2) | 2 | 2 | 2 |
| 16-Bit Timers (TMR0/1) | 1/2 | 1/2 | 1/2 |
| 16-Bit Universal Timer (UTMR) | 2 | 2 | 2 |
| 16-Bit Dual PWM | 2 | 2 | 2 |
| Capture/Compare/PWM (CCP) | 1 | 1 | 1 |
| Complementary Waveform Generator (CWG) | 1 | 1 | 1 |
| Numerically Controlled Oscillator (NCO) | 1 | 1 | 1 |
| Data Signal Modulator (DSM) | 1 | 1 | 1 |
| Configurable Logic Block (CLB) | 1 | 1 | 1 |
| Configurable Logic Cell (CLC) | 8 | 8 | 8 |
| 10-Bit Analog-to-Digital Converter with Computation (ADCC) External Channels | 19 | 22 | 30 |
| High/Low-Voltage Detect (HLVD) | 1 | 1 | 1 |
| High-Speed Analog Comparator (CMP) | 2 | 2 | 2 |
| Zero-Cross Detect (ZCD) | 1 | 1 | 1 |
| 8-Bit Digital-to-Analog Converter (DAC) | 1 | 1 | 1 |
| Serial Peripheral Interface (SPI) | 1 | 1 | 1 |
| Inter-Integrated Circuit (I2C) | 1 | 1 | 1 |
| Universal Asynchronous Receiver Transmitter (UART) | 1 | 1 | 1 |
| UART with Protocol Support | 1 | 1 | 1 |
| Direct Memory Access (DMA) Channels | 4 | 4 | 4 |
| Windowed Watchdog Timer (WWDT) | Yes | Yes | Yes |
| 32-Bit CRC with Scanner | Yes | Yes | Yes |
| Vectored Interrupts | Yes | Yes | Yes |
| Interrupt-on-Change (IOC) | Yes | Yes | Yes |
| Peripheral Module Disable (PMD) | Yes | Yes | Yes |
| Temperature Indicator | Yes | Yes | Yes |