25 CLB - Configurable Logic Block
The Configurable Logic Block (CLB) is a collection of logic elements that can be programmed to perform a wide variety of digital logic functions. The logic function may be completely combinatorial, sequential, or a combination of the two, enabling users to incorporate hardware-based custom logic into their applications.
- Interconnected fabric containing
128 Basic Logic Elements (BLE)
- Each BLE consists of one 4-input 16-value Look-up Table (LUT), a Flip-Flop, a mux for combinational or registered result, and an AND gate to zero the output when the module is in Reset
- Selectable clock sources with
configurable clock divider
- One PPS clock input pin
- Up to eight PPS inputs
- Up to sixteen PPS outputs with read-lock
- CLB Auto Configuration:
- Can be automatically configured during system boot
- Allows for CLB operation without CPU
- CLB hardware debugging outputs
- DMA compatible
The CLB module consists of two sets of register interfaces: the standard Special Function Register (SFR) interface, and the Microchip CLB Synthesizer.
These SFRs allow user software the ability to enable the module, program input bits into the CLB memory, select a clock source and clock divider, read the BLE outputs, and select specific BLE outputs for debugging purposes.
The Microchip CLB Synthesizer allows for complete configuration of the CLB module. Configuration data for the CLB is written from Program Memory through the NVM Scanner Module. The Interface does not appear as SFRs in the Register Map and is not directly user-accessible; it is accessible only through a programming system such as Microchip MPLAB® Tools for VS Code® that support programming the CLB.