22.2 PPS Inputs

Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register, with which the input pin to the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while devices with 28 leads or more allow PPS routing to I/Os contained within two ports, with the exception of the following signals, which are routed to three ports:
  • SPI1SCKPPS
  • SPI1SDIPPS
  • I2C1SCLPPS
  • I2C1SDAPPS
  • CLBINxPPS
  • CLBCLKPPS

The outputs of the Signal Routing Port (SRPORT) can also be used as inputs to other peripherals using PPS (see the table below).

Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier. For example, xxx = T0CKI for the T0CKIPPS register.

Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.

Table 22-1. PPS Input Selection Table
PeripheralPPS Input RegisterDefault Pin Selection at PORRegister Reset Value at PORAvailable Input Port
CLBOUTL/H28-Pin Devices40-Pin Devices48-Pin Devices
Interrupt 0INT0PPSRB0‘b0000 1000CLBOUTLAB—WAB———WAB————W
Interrupt 1INT1PPSRB1‘b0000 1001CLBOUTLAB—WAB———W—B—D——W
Interrupt 2INT2PPSRB2‘b0000 1010CLBOUTLAB—WAB———W—B———FW
Timer0 ClockT0CKIPPSRA4‘b0000 0100CLBOUTHAB—WAB———WA————FW
Timer1 ClockT1CKIPPSRC0‘b0001 0000CLBOUTHA—CWA—C——W——C—E—W
Timer1 GateT1GPPSRB5‘b0000 1101CLBOUTH—BCW—BC——W—BC———W
Timer3 ClockT3CKIPPSRC0‘b0001 0000CLBOUTL—BCW—BC——W——C—E—W
Timer3 GateT3GPPSRC0‘b0001 0000CLBOUTLA—CWA—C——WA—C———W
Timer2 InputT2INPPSRC3‘b0001 0011CLBOUTHA—CWA—C——WA—C———W
Timer4 InputT4INPPSRC5‘b0001 0101CLBOUTH—BCW—BC——W—BC———W
Universal Timer Input 0TUIN0PPSRC0‘b0001 0000CLBOUTHA—CW——C—EW——C—E—W
Universal Timer Input 1TUIN1PPSRB5‘b0000 1101CLBOUTH—BCW—BC——W—B———F—W
CCP1CCP1PPSRC2‘b0001 0010CLBOUTL—BCW—BC——W——C——FW
PWM Input 0PWMIN0PPSRC2‘b0001 0010CLBOUTL—BCW—BC——W——C——FW
PWM Input 1PWMIN1PPSRC1‘b0001 0001CLBOUTL—BCW—BC——W——C——FW
PWM1 External Reset SourcePWM1ERSPPSRC3‘b0001 0011CLBOUTLA—CWA—C——WA—C——W
PWM2 External Reset SourcePWM2ERSPPSRC5‘b0001 0101CLBOUTLA—CWA—C——W——C—E—W
CWG1CWG1PPSRB0‘b0000 1000CLBOUTL—BC——B—D———B—D———
CLCx Input 1CLCIN0PPSRA0‘b0000 0000CLBOUTL/HA—CWA—C——WA—C———W
CLCx Input 2CLCIN1PPSRA1‘b0000 0001CLBOUTL/HA—CWA—C——WA—C———W
CLCx Input 3CLCIN2PPSRB6‘b0000 1110CLBOUTL/H—BCW—B—D—W—B—D——W
CLCx Input 4CLCIN3PPSRB7‘b0000 1111CLBOUTL/H—BCW—B—D—W—B—D——W
CLCx Input 5CLCIN4PPSRA0‘b0000 0000CLBOUTL/HA—CWA—C——WA—C———W
CLCx Input 6CLCIN5PPSRA1‘b0000 0001CLBOUTL/HA—CWA—C——WA—C———W
CLCx Input 7CLCIN6PPSRB6‘b0000 1110CLBOUTL/H—BCW—B—D—W—B—D——W
CLCx Input 8CLCIN7PPSRB7‘b0000 1111CLBOUTL/H—BCW—B—D—W—B—D——W
ADC Conversion TriggerADACTPPSRB4‘b0000 1100CLBOUTH—BCW—B—D—W—B—D——W
SPI1 ClockSPI1SCKPPSRC3‘b0001 0011CLBOUTH—BCW—BCD—W—BCD——W
SPI1 DataSPI1SDIPPSRC4‘b0001 0100CLBOUTH—BCW—BCD—W—BCD——W
SPI1 Client SelectSPI1SSPPSRA5‘b0000 0101CLBOUTHA—CWA——D—WA——D——W
I2C1 ClockI2C1SCLPPS(1)RC3‘b0001 0011CLBOUTH—BC——BCD———BCD———
I2C1 DataI2C1SDAPPS(1)RC4‘b0001 0100CLBOUTH—BC——BCD———BCD———
UART1 ReceiveU1RXPPSRC5‘b0001 0101CLBOUTH—BCW—BC——W——C——FW
UART1 Clear to SendU1CTSPPSRC6‘b0001 0110CLBOUTH—BC——BC—————C——F—
UART1 ReceiveU2RXPPSRB7‘b0000 1111CLBOUTH—BCW—B—D—W—B—D——W
UART2 Clear to SendU2CTSPPSRB6‘b0000 1110CLBOUTH—BC——B—D———B—D———
Signal Routing Port Input 0PORTWIN0PPSRB2‘b0000 1010CLBOUTLAB———B—D———B—D———
Signal Routing Port Input 1PORTWIN1PPSRB0‘b0000 1000CLBOUTLAB———B—D———B—D———
Signal Routing Port Clock InputPORTWCLKPPSRB1‘b0000 1001CLBOUTLAB———B—D———B—D———
DSM Modulation Carrier HighMD1CARLPPSRA3‘b0000 0011CLBOUTL/HA—CWA——D—WA——D——W
DSM Modulation Carrier LowMD1CARHPPSRA4‘b0000 0100CLBOUTL/HA—CWA——D—WA——D——W
DSM Modulation SourceMD1SRCPPSRA5‘b0000 0101CLBOUTL/HA—CWA——D—WA——D——W
CLB Input 0CLBIN0PPSRC0‘b0001 0000—A—C—A—CD——A—CD———
CLB Input 1CLBIN1PPSRC1‘b0001 0001—A—C—A—CD——A—CD———
CLB Input 2CLBIN2PPSRC2‘b0001 0010—A—C—A—CD——A—CD———
CLB Input 3CLBIN3PPSRC3‘b0001 0011—A—C—A—CD——A—CD———
CLB Input 4CLBIN4PPSRC4‘b0001 0100—A—C—A—CD——A—CD———
CLB Input 5CLBIN5PPSRC5‘b0001 0101—A—C—A—CD——A—CD———
CLB Input 6CLBIN6PPSRC6‘b0001 0110—A—C—A—CD——A—CD———
CLB Input 7CLBIN7PPSRA0‘b0000 0000—A—C—A—CD——A—CD———
CLB ClockCLBCLKPPSRA1‘b0000 0001—A—C—A—CD——A—CD———
Note:
  1. Bidirectional pin. The corresponding output must select the same pin.