2.1 Write Configuration into Registers (Optional)

Table 2-1 lists a series of parameters that must be configured with the given values and in the order listed. These settings must be configured for optimal performance and compliance to OPEN Alliance specifications.

Among the parameters is the Link Status Control (LSCTL, Address=0x0012) Register, which was introduced in silicon revision D0 and is defined in the LAN8670/1/2 10BASE‑T1S Ethernet PHY Transceiver Datasheet. This register defines how link status is derived on the PHY. The user may decide which of the described methods best suits their application and which pin output may signal the current link status by writing the corresponding settings into the register.

Table 2-1. Configuration Register Writes
Access	MMD	Address	Writes
W	0x1F	0x0037	0x0800
W	0x1F	0x008A	0xBFC0
W	0x1F	0x0118	0x029C
W	0x1F	0x00D6	0x1001
W	0x1F	0x0082	0x001C
W	0x1F	0x00FD	0x0C0B¹
W	0x1F	0x00FD	0x8C07¹
W	0x1F	0x0091	0x9660
W	0x1F	0x0012 (LSCTL)	0xXXXX²
Note: It is important to write both values shown in this table to this register, one after the other. The user may select how Link Status is derived and which pin indicates its status. To provide backwards compatibility with earlier revision devices, the same behavior as earlier revision devices can be achieved in revision D0 devices and later by selecting no pin output and forcing Link Status to always return a ‘1’ by writing ‘0x1001’ into the LSCTL register.