1 Peripheral Overview

The Analog-to-Digital Converter with Computation (ADCC) and Context Switching is a peripheral that allows reading an analog voltage, converts it into a digital value, and offers the option to add various computation procedures to the result. It can be used in single-ended conversions, measuring the voltage between the selected analog input and VSS (0V), or in differential conversions, measuring the voltage difference between two analog input channels chosen by the user.

The ADCC with Context Switching has a variety of positive and negative input channels. The selection for the positive input channel is realized by writing in the ADC Positive Channel Selection Register (ADPCH), and for selecting a negative input channel by writing in the ADC Negative Channel Selection Register (ADNCH). Some of the available input channels are Fixed Voltage Reference (FVR) buffers, Digital-to-Analog Converter (DAC) output, Operational Amplifier (OPA) output, or external pins.

The ADCC with Context Switching can have different positive and negative voltage references. The positive reference can be chosen by writing the ADC Positive Voltage Reference Selection (PREF) bits of the ADC Reference Selection (ADREF) register. The available sources are the FVR module output, the external VREF+, or the supply voltage (VDD). The negative reference can be selected from the external VREF- or AVSS by writing the ADC Negative Voltage Reference Selection (NREF) bit in the same register as above.

The ADCC with Context Switching can use two different clock sources. The dedicated ADCRC oscillator supplies one clock source, while the other one is derived from the main oscillator with the possibility of using a prescaler. The ADC Clock Selection (CS) bit value in the ADC Control 0 (ADCON0) register selects the clock source. Depending on the prescaler selection and clock source selection, the conversion time can be outside the limits, and the ADCC with Context Switching will not be able to perform a conversion. For further details on the appropriate conversion timings, refer to the device data sheet.

Figure 1-1. ADCC with Context Switching Block Diagram

The results from the ADCC with Context Switching conversions can be provided either right- or left-justified, depending on the ADC Results Format/Alignment Selection (FM) bits in the ADC Control 0 (ADCON0) register. The bit field above controls the result format: Sign/magnitude or two’s complement format.

The ADCC with Context Switching can perform conversions on a trigger signal. The trigger signal comes from an external pin or other peripherals. The Auto-Conversion Trigger Select (ACT) bit field in the ADC Auto-Conversion Trigger Source Selection (ADACT) register controls the selected trigger source. The timing requirements for a conversion still need to be followed (e.g., if a conversion takes 100 µs, then a trigger that comes faster than 100 µs will not produce a new conversion).

To enable the ADCC with Context Switching peripheral, the ADC Enable (ON) bit in the ADC Control 0 (ADCON0) register needs to be set. Any of the following events may start a conversion: The software setting of the ADC Conversion Status (GO) bit in the ADCON0 register, a trigger signal configured in the ADACT register or a Continuous mode retrigger, by setting the ADC Continuous Operation Enable (CONT) bit in the ADCON0 register.

The ADCC with Context Switching peripheral is equipped with post-conversion computation features that can be configured through the ADC Operating Mode Selection (MD) bit field in the ADC Control 2 (ADCON2) register. There are five available computation modes:

  • Basic (Legacy) mode: The normal conversion mode. A single or double conversion is done, and the result is stored in the ADC Result (ADRES) register. A threshold error comparison can be configured and performed.
  • Accumulate mode: After each trigger, the conversion result is added to the accumulator and the value in the ADC Repeat Counter (ADCNT) register is incremented.
  • Average mode: After each trigger, the conversion result is added to the accumulator. A threshold test is performed when a certain number of samples have been acquired, with the number being defined by the ADC Repeat Setting (ADRPT) register.
  • Burst Average mode: This mode is similar to the Average one – every conversion is counted, and the result is added to an accumulator register. The conversions are retriggered until the Repeat Setting (RPT) samples are accumulated, and finally a threshold test is performed.
  • Low-Pass Filter mode: This mode works the same as the Average one – every conversion is counted and the result is added to an accumulator register. When the number of required samples is met, it performs a low-pass filtering operation on all of them, removing those affected by noise and then performing a threshold comparison on the result.

Refer to the device data sheet for further details on ADCC with Context Switching computation modes.

The ADCC with Context Switching module contains several features that allow the user to perform a relative capacitance measurement on any input channel, using the internal Sample-and-Hold (S/H) capacitance as reference. This relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. The ADCC with Context Switching also features two guard ring drive outputs, which help minimize the effects of the parasitic capacitance.

The ADCC with Context Switching features a Channel Sequencer and Context that automates context saving and channel sequencing. This feature is used to reduce software overhead when the peripheral is using multiple input channels by transferring the active channel context configuration from memory into the associated registers and performing the desired conversion. The channel context is used to save a set of control, status, and data register configurations, which define a conversion and its settings. The channel sequencer automatically performs the operations defined by each channel context.