1.2 Start, Reset and Stop Hardware Limit Timing

The UTMR module consists of an External Reset Signal (ERS) source that can be used to Start, Reset and/or Stop the timer without any software intervention. The different Start, Reset and Stop conditions are listed in the tables below. The EPOL bit controls the polarity of the ERS signal and changes how the Start, Reset, and Stop conditions are handled in the hardware.
Table 1-1. Start Conditions
Start ConditionOperation when EPOL = 0Operation when EPOL = 1
NoneNo hardware control – timer runs when ON = 1Same as EPOL = 0
Either ERS EdgeTimer starts at either edge (rising or falling) of ERSSame as EPOL = 0
Rising ERS EdgeTimer starts at rising edge of ERSTimer starts at falling edge of ERS
ERS Level-1Timer starts at the first clock where ERS has a high level and the Start condition remains asserted as long as the subsequent clocks register a high ERS level.Timer starts at the first clock where ERS has a low level and the Start condition remains asserted as long as the subsequent clocks register a low ERS level.
Table 1-2. Reset Conditions
Reset ConditionOperation when EPOL = 0Operation when EPOL = 1
NoneNo hardware resetSame as EPOL = 0
ERS Level-0 + PR Match

Timer resets at the first clock where ERS has a low level and the Reset condition remains asserted as long as the subsequent clocks register a low ERS level. Level output and RUN bit become false while the Reset condition is active.

A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in this case.

Timer resets at the first clock where ERS has a high level and the Reset condition remains asserted as long as the subsequent clocks register a high ERS level. Level output and RUN bit become false while the Reset condition is active.

A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in this case.
At Start + PR MatchTimer resets at the first clock whenever a Start condition is generated. A PR match condition also triggers a Reset, in which case the timer resets at the next clock after PR match. Level output and RUN bit remain true in either case.Same as EPOL = 0
At PR MatchTimer resets at the next clock after a PR match condition is generated. Level output and RUN bit remain true in this case.Same as EPOL = 0
Table 1-3. Stop Conditions
Reset ConditionOperation when EPOL = 0Operation when EPOL = 1
NoneNo hardware control – timer stops when ON = 0. Capture occurs at every rising ERS edge.No hardware control – timer stops when ON = 0. Capture occurs at every falling ERS edge.
Either ERS EdgeTimer stops at either edge (rising or falling) of ERS and causes a capture eventSame as EPOL = 0
Rising ERS EdgeTimer stops at rising edge of ERS and causes a capture event.Timer stops at falling edge of ERS and causes a capture event
At PR MatchTimer stops at the next clock after a PR match condition occurs and causes a capture event.Same as EPOL = 0