1.3 Synchronous vs. Asynchronous Operation

The UTMR module is designed to operate completely isolated from the main system which simplifies the timing, especially when running off of an external clock. The timer being isolated means that any input or output signal or command needs to be synchronized to the timer domain. This synchronization is controlled by the CSYNC bit.

When the CSYNC bit is set, any input signal or command that goes from the system domain into the timer domain is synchronized to the timer clock, and any output signal that goes from the timer domain to the system domain is synchronized to the system clock. There will be a synchronization delay of up to three cycles of the clock that the signal is being synchronized to, i.e., an input signal or command will be delayed by three timer clocks, whereas an output signal will be delayed by three system clocks. This synchronization ensures that any ERS edges or SFR bit changes are not missed by the timer. Because the delay is the same for any Start, Reset or Stop condition, the counter value of the timer will remain unaffected. See Figure 1-1 and Figure 1-2 for examples of clock synchronization.

Figure 1-1. Clock Synchronization with ON bit and Stop Condition

Figure 1-2. Clock Synchronization with ON bit and Off Condition

When the CSYNC bit is cleared, all input signals and commands are fed directly into the timer module, and all output signals go to the system domain immediately. There is no synchronization delay because the signals are registered immediately. If the edge of the input signal or command occurs too close to the active clock edge, a clock collision may occur and there is a chance that the input signal or command will be missed. To avoid this, consider setting CSYNC = 1 to synchronize the signals. Use of CSYNC = 0 is only recommended when the clock is non-continuous (like push button, or a counter) and it is expected that the clock and ERS edges won’t collide.