15.3.2.3 Event Generators

Each event channel has several possible event generators, but only one can be selected at a time. The event generator for a channel is selected by writing to the respective Channel n Generator Selection (EVSYS.CHANNELn) register. By default, the channels are not connected to any event generator. For details on event generation, refer to the documentation of the corresponding peripheral.

A generated event is either synchronous or asynchronous to the device peripheral clock (CLK_PER). Asynchronous events can be generated outside the normal edges of the peripheral clock, making the system respond faster than the selected clock frequency would suggest. Asynchronous events can also be generated while the device is in a sleep mode when the peripheral clock is not running.

Any generated event is classified as either a pulse event or a level event. In both cases, the event can be either synchronous or asynchronous, with properties according to the table below.

Table 15-1. Properties of Generated Events
Event TypeSync/AsyncDescription
PulseSyncAn event generated from CLK_PER that lasts one clock cycle
AsyncAn event generated from a clock other than CLK_PER lasting one clock cycle
LevelSyncAn event generated from CLK_PER that lasts multiple clock cycles
AsyncAn event generated without a clock (for example, a pin or a comparator), or an event generated from a clock other than CLK_PER that lasts multiple clock cycles

The properties of both the generated event and the intended event user must be considered in order to ensure reliable and predictable operation.

The table below shows the available event generators for this device family.

Generator NameDescriptionEvent TypeGenerating Clock DomainLength of event
PeripheralEvent
UPDISYNCHSYNCH characterLevelCLK_PDISYNCH character on PDI RX input synchronized to CLK_PDI
RTCOVFOverflowPulseCLK_RTCOne CLK_RTC period
CMPCompare Match
PIT_DIV8192Prescaled RTC clock divided by 8192LevelGiven by prescaled RTC clock divided by 8192
PIT_DIV4096Prescaled RTC clock divided by 4096Given by prescaled RTC clock divided by 4096
PIT_DIV2048Prescaled RTC clock divided by 2048Given by prescaled RTC clock divided by 2048
PIT_DIV1024Prescaled RTC clock divided by 1024Given by prescaled RTC clock divided by 1024
PIT_DIV512Prescaled RTC clock divided by 512Given by prescaled RTC clock divided by 512
PIT_DIV256Prescaled RTC clock divided by 256Given by prescaled RTC clock divided by 256
PIT_DIV128Prescaled RTC clock divided by 128Given by prescaled RTC clock divided by 128
PIT_DIV64Prescaled RTC clock divided by 64Given by prescaled RTC clock divided by 64
CCL LUTnLUT output levelLevelAsynchronousDepends on CCL configuration
ACnOUTComparator output levelLevelAsynchronousGiven by AC output level
ADCnRESRDYResult readyPulseCLK_PEROne CLK_PER period
PTCRESRDYResult readyPulseCLK_PEROne CLK_PER period
ZCDnOUTZCD output levelLevelAsynchronousGiven by ZCD output level
PORTxPINnPin levelLevelAsynchronousGiven by pin level
USARTnXCKUSART Baud clockLevelCLK_PERMinimum two CLK_PER periods
SPInSCKSPI Host clockLevelCLK_PERMinimum two CLK_PER periods
TCAnOVF_LUNFOverflow/Low byte timer underflowPulseCLK_PEROne CLK_PER period
HUNFHigh byte timer underflow
CMP0_LCMP0Compare channel 0 match/Low byte timer compare channel 0 match
CMP1_LCMP1Compare channel 1 match/Low byte timer compare channel 1 match
CMP2_LCMP2Compare channel 2 match/Low byte timer compare channel 2 match
TCBnCAPTCAPT flag setPulseCLK_PEROne CLK_PER period
OVFOverflow
TCDnCMPBCLRCounter matches CMPBCLRPulseCLK_TCDOne CLK_TCD period
CMPASETCounter matches CMPASET
CMPBSETCounter matches CMPBSET
PROGEVProgrammable event output