Figure 38-111. Gain Error vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V)
Figure 38-112. Gain Error vs.
Sample Rate (ADC Single Ended Mode, VREFA =
VDD = 3.0V)
Figure 38-113. Offset Error
vs. VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V)
Figure 38-114. Offset Error
vs. Sample Rate (ADC Single Ended Mode, VREFA =
VVDD = 3.0V)
Figure 38-115. DNL vs. ADC
code (ADC Single Ended Mode @60 ksps, VDD =
3.0V)
Figure 38-116. INL vs. ADC
code (ADC Single Ended Mode @60 ksps, VDD =
3.0V)
Figure 38-117. DNL vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V, T = 125°C)
Figure 38-118. DNL vs. Sample
Rate (ADC Single Ended Mode, VREFA = VDD =
3.0V, T = 125°C)
Figure 38-119. INL vs.
VREFA (ADC Single Ended Mode @60 ksps,
VDD = 3.0V, T = 125°C)
Figure 38-120. INL vs. Sample
Rate (ADC Single Ended Mode, VREFA = VDD =
3.0V, T = 125°C)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
