22.3.3.1.7 Single-Shot Mode

Use the Single-Shot mode to generate a pulse with a duration defined by the Capture/Compare (TCBn.CCMP) register every time a rising or falling edge is observed on a connected event channel.

This mode requires TCB to be configured as an event user and is explained in the Events section.

When the counter stops, the output pin is set low. If an event is detected on the connected event channel, the TCB peripheral will reset and start counting from BOTTOM to TOP while driving its output high. Read the Run ( RUN) bit in the Status (TCBn.STATUS) register to see if the counter is counting. Once the value of CNT reaches the TCBn.CCMP register, the counter ceases counting. Simultaneously, the output pin transitions to a low state for at least one counter-clock cycle (TCB_CLK). During this period, any new event that occurs is disregarded. Following this, there is a two peripheral clock cycles (PER_CLK) delay before the output is set high after receiving a new event.

Writing a ‘1’ to the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register triggers any edge to start the counter.

Writing a ‘0’ to the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register triggers only positive edges to start the counter.

The counter starts counting as soon as the peripheral is enabled, even without triggering by an event or if the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register is modified while the peripheral is enabled, which is prevented by writing TOP to the Counter (TCBn.CNT) register. A similar behavior is seen if the Event Edge (EDGE) bit in the Event Control (TCBn.EVCTRL) register is ‘1’ while the module is enabled. Writing TOP to the Counter (TCBn.CNT) register prevents this.

Writing a ‘1’ to the Event Asynchronous (ASYNC) bit in the Control B (TCBn.CTRLB) register, the TCB peripheral reacts asynchronously to an incoming event. An edge on the event will immediately cause the output signal to be set. The counter will still start counting two complete clock cycles after receiving the event, resulting in an observed delay of two to three clock cycles.