16.5 Debug and Test Pin Description

Table 16-1. Debug and Test Signal List
Signal Name	Function	Type	Active Level
Reset/Test
NRST	Microcontroller Reset	Input/Output	Low
TST	Test Select	Input	–
Serial Wire Debug Port/JTAG Boundary Scan
TCK/SWCLK	Test Clock/Serial Wire Clock	Input	–
TDI	Test Data In	Input	–
TDO/TRACESWO	Test Data Out/Trace Asynchronous Data Out	Output	–
TMS/SWDIO	Test Mode Select/Serial Wire Input/Output	Input	–
JTAGSEL	JTAG Selection	Input	High
Trace Debug Port
TRACECLK	Trace Clock	Output	–
TRACED0–3	Trace Data	Output	–

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