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35.4 DMA Controller Peripheral Connections Table 35-1. Peripheral Hardware Requests Peripheral Name Transfer Type HW Interface Number (XDMAC_CC.PERID) HSMCI Transmit/Receive 0 SPI0 Transmit 1 SPI0 Receive 2 SPI1 Transmit 3 SPI1 Receive 4 QSPI Transmit 5 QSPI Receive 6 USART0 Transmit 7 USART0 Receive 8 USART1 Transmit 9 USART1 Receive 10 USART2 Transmit 11 USART2 Receive 12 PWM0 Transmit 13 TWIHS0 Transmit 14 TWIHS0 Receive 15 TWIHS1 Transmit 16 TWIHS1 Receive 17 TWIHS2 Transmit 18 TWIHS2 Receive 19 UART0 Transmit 20 UART0 Receive 21 UART1 Transmit 22 UART1 Receive 23 UART2 Transmit 24 UART2 Receive 25 UART3 Transmit 26 UART3 Receive 27 UART4 Transmit 28 UART4 Receive 29 DACC Transmit 30 SSC Transmit 32 SSC Receive 33 PIOA Receive 34 AFEC0 Receive 35 AFEC1 Receive 36 AES Transmit 37 AES Receive 38 PWM1 Transmit 39 TC0.Ch0 Receive 40 TC1.Ch0 Receive 41 TC2.Ch0 Receive 42 TC3.Ch0 Receive 43 I2SC0 Transmit Left 44 I2SC0 Receive Left 45 I2SC1 Transmit Left 46 I2SC1 Receive Left 47 I2SC0 Transmit Right 48 I2SC0 Receive Right 49 I2SC1 Transmit Right 50 I2SC1 Receive Right 51
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