6 Interrupts

Source and Destination Count Interrupt:

The Source Count Interrupt Flag (DMAxSCNTIF) and Destination Count Interrupt Flag (DMAxDCNTIF) are set when the corresponding count registers (DMAxSCNT and DMAxDCNT) are reloaded. This signifies that the message transfer is complete.

Abort Interrupt:

The Abort Interrupt Flag bit (DMAxAIF) is set when an abort trigger is received and the AIRQEN bit is set.

Overrun Interrupt:

The Overrun Interrupt Flag bit (DMAxORIF) is set when a new hardware trigger is received before the previous transaction is completed. This overrun condition does not affect the DMA operation, but is used to indicate that the DMA module may not be able to keep up with the DMA requests.