1 System Operation

As shown in Figure , each DMA controller can be independently configured to move data between single or multiple addresses. The DMA controllers use the same instruction bus and data bus as the CPU for transferring data between memories. Depending on the priority set in the system arbiter, the DMA controller can move data either by utilizing unused CPU cycles or stalling the CPU. By default, the CPU has priority over DMA. In this case, the DMA steals unused cycles from the CPU to perform the read/write operations. Because of this concurrent operation between the CPU and DMA, the bandwidth of handling data is increased and the DMA module can operate in the background.