1.5.2.1 How the Library Works

The PRIME Reset Handler service library offers the necessary functions to manage fault interrupt handlers, to store reset information and to trigger software resets.

This library needs to be initialized, but it does not need to be maintained periodically.

Reset Handling

The following fault interrupt handlers are implemented in the PRIME Reset Handler library:

Hard Fault
Memory Management
Bus Fault
Usage Fault
Watchdog

When an error interrupt is triggered, this library stores the value of several registers, the number of resets and the reset type.

On the Arm Cortex-M0+ devices, such as the SAMD20, only the Hard Fault and Watchdog handlers are implemented; the Memory Management, Bus Fault and Usage Fault exceptions do not exist on the Arm Cortex-M0+ and escalate to a Hard Fault.

Note that the information stored and the storage used depend on the hardware platform and the PRIME node:

For PIC32CXMT devices:
Table 1-14. PIC32CXMT Reset Information in Service Node
GPBR Contents
5 number of resets + reset type
6 PC
7 LR
8 PSR
9 HFSR
10 CFSR
11 R0
12 R1
13 R2
14 R3
Table 1-15. PIC32CXMT Reset Information in Base Node
GPBR Contents
0 number of resets + reset type
1 PC
2 LR
3 PSR
4 HFSR
5 CFSR
6 R0
7 R1
8 R2
9 R3
10 R12

Table 1-15. PIC32CXMT Reset Information in Base Node
GPBR	Contents
0	number of resets + reset type
1	PC
2	LR
3	PSR
4	HFSR
5	CFSR
6	R0
7	R1
8	R2
9	R3
10	R12

For SAME70 devices:
Table 1-16. SAME70 Reset Information in Slave Service Node
GPBR Contents
5 number of resets + reset type
6 PC
7 LR
Table 1-17. SAME70 Reset Information in Base Node
GPBR Contents
0 number of resets + reset type
1 PC
2 LR
3 PSR
4 HFSR
5 CFSR
6 R0
7 R1

Table 1-17. SAME70 Reset Information in Base Node
GPBR	Contents
0	number of resets + reset type
1	PC
2	LR
3	PSR
4	HFSR
5	CFSR
6	R0
7	R1

For SAMD20 devices, the reset information is stored in the emulated EEPROM through the Storage service non-volatile data slots (the SAMD20 has no GPBRs):

Table 1-18. SAMD20 Reset Information in Service Node
Slot	Contents
5	number of resets + reset type
6	PC
7	LR
8	PSR
9	HFSR (always 0 on Arm Cortex-M0+)
10	CFSR (always 0 on Arm Cortex-M0+)
11	R0
12	R1
13	R2
14	R3
15	R12

For other MCU devices, it is not implemented yet

Reset Sources

There are different reset types (see SRV_RESET_HANDLER_RESET_CAUSE Enum), which combine device reset sources and PRIME-specific sources.

PIC32CXMT

On PIC32CXMT devices, the reset type is read at initialization from the RSTC driver.

Reset sources 0–4 are already defined in the RSTC driver:

GENERAL_RESET: No information is available because this is the first power-up.
BACK_RESET and USER_RESET: The only information available is the reset type and the number of resets because the handlers are not invoked and therefore the GPBRs have not been updated.
WATCHDOG_RESET: When the watchdog has been configured to trigger a reset instead of an interrupt, the only information available is the reset type and the number of resets because the handlers are not invoked and therefore the GPBRs have not been updated.
SOFTWARE_RESET: If a software reset is triggered by the user application, the only information available is the reset type because the handlers are not invoked and therefore the GPBRs have not been updated. The number of resets is not updated.

The reset source FU_RESET is set during a firmware upgrade process in the PRIME Service Node and does not invoke the handlers. Therefore, the only information available is the reset type and the number of resets.

For the rest of reset sources, there is information available in the GPBRs.

SAMD20

On the SAMD20, the reset type is not read from a reset controller. It is recorded only when one of the service handlers runs — a Hard Fault (RESET_HANDLER_HARD_FAULT_RESET) or a watchdog early-warning (RESET_HANDLER_WATCHDOG_RESET) — or when the application requests a reset through SRV_RESET_HANDLER_RestartSystem (for example, RESET_HANDLER_SOFTWARE_RESET or RESET_HANDLER_FU_RESET). In those cases the reset type, the number of resets and, for a Hard Fault, the fault context are stored in the emulated EEPROM (see the table above). Resets that do not go through a handler or through SRV_RESET_HANDLER_RestartSystem, such as a power-on reset or an external reset on the NRST pin, are not classified.