2 Frequency Domain: Phase Noise Jitter Measurements

Phase noise is often considered an important measurement of spectral purity, which is the inherent stability of a timing signal. Let’s take a sinusoidal oscillator that outputs a sine wave with a frequency Fc. An ideal oscillator will have perfect spectral purity, with all of its power concentrated at Fc. As jitter causes variations in frequency, this results in power being spread out to adjacent frequencies, creating sidebands. By measuring the amount of power in the sidebands relative to the carrier, we can derive a jitter value.

Phase jitter can be calculated by measuring the phase spectral density of the clock’s signal and integrating over a specific frequency band of interest. The area under the spectrum plot represents the power level of the phase modulating (jitter producing) noise and the power of the noise is proportional to the RMS phase jitter squared. In most cases, the upper frequency can be specified up to the Nyquist frequency of the system. An application may only be interested in a range of the phase noise plot and typically will specify that range or apply a mask to identify the area of interest and maximum dBc values permitted. This mask is often called a Jitter Mask.

In order to specify a Jitter Mask, a system’s transfer function must be analyzed. The jitter mask will specify the clock performance in how it will actually affect the system, with the goal of avoiding over-specification. In today’s engineering world, many jitter masks have been predetermined by industry protocols, the most common being the requirement for SONET (12kHz to 20MHz) and related telecom standards for optical carrier network OC48. This jitter mask has become an unofficial industry standard, regardless of whether or not the clock will be used in a SONET application.

This can be problematic, as it is not always the case that the 12 kHz to 20 MHz jitter bandwidth can be measured, or even make sense, if the carrier or clock frequency is too low. Practical systems have digital sampling, or equivalent mixing and filtering limitations, that require the minimum carrier frequency to be roughly 2X or more than the maximum offset frequency. Even if this was not the case, one cannot measure a clock with a carrier frequency <20MHz directly with offsets out to 20MHz. It is for this reason that a designer (both for the oscillator and the system) must have a firm understanding of what exactly they are asking for when it comes to a phase jitter specification.