The Controller uses the Direct and Broadcast ENEC/DISEC set of CCCs to control whether
Target-initiated traffic is allowed on the bus or not. This governs whether a Target on
the bus can perform any of following three requests:
Figure 37-22 shows the frame format for Direct Write
ENEC/DISEC CCC, whereas Figure 37-23 shows the frame
format for Broadcast Write ENEC/DISEC CCC. Table 37-12 and Table 37-13 show the
command byte for ENEC and DISEC respectively. The information received from the
Controller is stored in the I3CxEC Event Commands register.
Table 37-12. Enable Target Events Command Byte
Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ENHJ
Reserved
ENCR
ENINT
Table 37-13. Disable Target Events Command Byte
Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DISHJ
Reserved
DISCR
DISINT
The ENINT/DISINT (IBIEN
bit in the I3CxEC register) allows the Controller to control when a Target can perform
an IBI request. When enabled (ENINT), the Controller instructs the Target that
performing IBI requests is permitted on the bus. When disabled (DISINT), the Controller
instructs the Target that performing IBI requests is not permitted on the bus and that
any such requests may not be honored.
The ENHJ/DISHJ (HJEN
bit in the I3CxEC register) allows the Controller to control when a Target can perform a
Hot-Join request. When enabled (ENHJ), the Controller instructs the Target that
performing Hot-Join requests is permitted on the bus. When disabled (DISHJ), the
Controller instructs the Target that performing Hot-Join requests is not permitted on
the bus and that any such requests may not be honored. The Controller can choose to
broadcast this CCC to instruct devices to refrain from making Dynamic Address Assignment
requests until later authorized by the Controller, in case the Controller is unable to
service the Hot-Joining devices.
Important: This I3C Target module
does not support Secondary Controller features. Controller role request (ENCR/DISCR) in
the command byte will be ignored and the CREN bit in the I3CxEC register will always read
‘0’.
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