1.1.2 Acquisition Time Cannot Be Changed through Either the ADACQ or the ADPRE Registers
ADC acquisition (sample) time cannot be modified by writing to either the ADPRE or ADACQ registers. Writes to the ADPRE or ADACQ registers will correctly delay the next conversion but will have no affect on increasing the actual sample time of the current conversion. For example, if the ADCRC is used as the clock source, the sample time will be nominally 3.33 μs, regardless of the values in either of the ADACQ or ADPRE registers.
Work around
There is essentially no work around for increasing the sample times via the ADPRE or
ADACQ registers; however, there are various work arounds and/or techniques that can
be implemented to acquire a more accurate ADC measurement.
- If the ADC is using the
FOSC, reducing the clock speed at the time of measurement
will increase the overall sampling time
- Use the NOSC/NDIV bits of OSCCON1 to reduce the oscillator speed
- Adjust the ADCLK divider value to reduce the oscillator speed
- Switch the ADC clock to the ADCRC
- The source input impedance (RS) directly effects the amount of time it takes to charge the CHOLD capacitor. Reducing the input impedance to a minimum will help reduce the sample time needed for the ADC measurement.
Affected Silicon Revisions
| B0 | B2 | B3 | B4 | ||||
| X | X |