6.3.2.1 NVM Sub-Layer
- Abstract the address for the EEPROM emulation area and the Flash storage are into logical address so that it is easy to combine both memories.
- Manage the integrity of the information stored.
- The Flash memory in SAM R34 is organized into pages and rows. The
following points explain how the NVM is organized:
- Each row has four pages.
- Data can be written once per page given a row. If writing is done more than once per page in a row, data gets corrupted. So, write granularity is page wise.
- Data can be erased for a row and not for a page. This means that data stored in all four pages will be erased. So, erase granularity is row wise.
- If data needs to be
re-written to a page in a row, first the row must be erased and then
data to that page can be written. The data stored in the other pages
will be lost due to erasure.
To prevent this, before issuing an erase, the row must be read to RAM and written back after erasure with the new data.
From the above points, the PDS module is designed in such a way that a row can be treated as the smallest possible NVM element that can be maintained with least possible code. In SAM R34, the size of the NVM Row is 256 bytes. In the NVM sub-layer, each row is given a logical row number in EEPROM Flash section or code Flash section. So, this abstraction manages the map that involves in the translation of logical row number to physical address. If more memory is required it can be added by updating this mapping table.
The integrity of the data storage is done by calculating the 16-bit CRC for the data to be stored. This calculated CRC is also stored along with the data in NVM, so that while reading back the integrity of the data can be checked.