1 Silicon Issue Summary

Legend

-: Erratum is not applicable.
X: Erratum is applicable.


Peripheral	Short Description	Valid for Silicon Revision
Peripheral	Short Description	Rev. B⁽¹⁾
Device	Writing the OSCLOCK Fuse in FUSE.OSCCFG to ‘1’ Prevents Automatic Loading of Calibration Values	X
Device	Write Operation Lost if Consecutive Writes to Specific Address Space	X
AC	Coupling Through AC Pins	X
	AC Interrupt Flag Not Set Unless Interrupt is Enabled	X
	False Triggers May Occur Under Certain Conditions	X
	False Triggering When Sweeping Negative Input of the AC When the Low-Power Mode is Disabled	X
ADC	One Extra Measurement Performed After Disabling ADC Free-Running Mode	X
	Changing ADC Control Bits During Free-Running Mode not Working	X
	ADC Wake-Up with WCMP	X
	ADC Functionality Cannot be Ensured with CLK_ADC Above 1.5 MHz and a Setting of 25% Duty Cycle	X
	ADC Performance Degrades with CLK_ADC Above 1.5 MHz and V_DD < 2.7V	X
	Pending Event Stuck When Disabling the ADC	X
	ADC Interrupt Flags Cleared When Reading RESH	X
CCL	Connecting LUTs in Linked Mode Requires OUTEN Set to ‘1’	X
	D-latch is Not Functional	X
	The CCL Must be Disabled to Change the Configuration of a Single LUT	X
NVMCTRL	Wrong Reset Value of NVMCTRL.CTRLA Register	X
RTC	Any Write to the RTC.CTRLA Register Resets the RTC and PIT Prescaler	X
RTC	Disabling the RTC Stops the PIT	X
TCA	Restart Will Reset Counter Direction in NORMAL and FRQ Mode	X
TCB	Minimum Event Duration Must Exceed the Selected Clock Period	X
	The TCB Interrupt Flag is Cleared When Reading CCMPH	X
	TCB Input Capture Frequency and Pulse-Width Measurement Mode Not Working with Prescaled Clock	X
	The TCA Restart Command Does Not Force a Restart of TCB	X
	CCMP and CNT Registers Act as 16-Bit Registers in 8-Bit PWM Mode	X
TCD	TCD Auto-Update Not Working	X
	TCD Event Output Lines May Give False Events	X
	Asynchronous Input Events Not Working When TCD Counter Prescaler is Used	X
	Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is ‘`0`’ or Dual Slope Mode is Used	X
TWI	TIMEOUT Bit Field in the TWIn.MCTRLA Register is Corrupted	X
	TWI Smart Mode Gives Extra Clock Pulse	X
	TWI Host Mode Wrongly Detects the Start Bit as a Stop Bit	X
	The TWI Host Enable Quick Command is Not Accessible	X
USART	TXD Pin Override Not Released When Disabling the Transmitter	X
	Frame Error on a Previous Message May Cause False Start Bit Detection	X
	Full Range Duty Cycle Not Supported When Validating LIN Sync Field	X
	Open-Drain Mode Does Not Work When TXD is Configured as Output	X

Note:

This revision is the initial release of the silicon.