50.5.4 Clock Formats

The SPI peripheral supports four different serial clock formats. The user software can select one of these formats by configuring the Clock Polarity Select bits (SPIxCTRL_*.CPOL) and the Clock Edge Select bits (SPIxCTRL_*.CPHA).

The CPOL bit determines whether the serial clock is at a high logic level or a low logic level when the SPI macro is in an Idle state.

  • If CPOL is set, the SCK signal is interpreted as ‘active-low’.
  • If CPOL is cleared, the SCK signal is interpreted as‘active-high’.

The CPHA bit determines whether the serial data output changes its state on an idle-to-active transition of the serial clock or on an active-to-idle transition of the serial clock. That is, CPHA=0 means sampling on the first clock edge, while CPHA=1 means sampling on the second clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle.

  • If CPHA is cleared, SDO changes on an active-to-idle transition.
  • If CPHA is set, SDO changes on an idle-to-active transition.
Note: The user must turn the macro off prior to changing the CPHA or CPOL bits; otherwise the behavior of the macro is not guaranteed.
Table 50-2. SPI Four Modes Combine Polarity and Phase
ModeCPOLCPHADescription
SPI_MODE000SPI_CLK is active high and sample commences on the rising edge
SPI_MODE101SPI_CLK is active high and sample commences on the falling edge
SPI_MODE210SPI_CLK is active low and sample commences on the rising edge
SPI_MODE311SPI_CLK is active low and sample commences on the falling edge

On the first write to SPIxBUF, the SPIxCTRL_*.SPITBE bit is cleared for a very short period of time; however, on the second write, it will stay cleared until the completion of the first transmission and the beginning of the next transmission, meaning that the data loaded cannot be transferred to SPIxSR until the previous transmission has completed. The macro will sample the incoming data (via SDI pin) as specified by the SPIxCTRL_*.SMP bit.

Figure 50-5. SPI Mode Timing (Host Mode; Mode16=0, Mode32=0, Mode_EN=0)

The 16-bit mode simply has more clock pulses than 8-bit mode.

Figure 50-6. SPI Mode Timing (Host Mode; Mode16=1, Mode32=0, Mode_EN=0)

The 32-bit mode simply has more clock pulses than 8-bit or 16-bit mode.

Figure 50-7. SPI Mode Timing (Host Mode; Mode32=1, Mode16=0/1, Mode_EN=0)