50.5.13 Audio Protocol I8S (I2S) (I2STPD) Operation New Features

The register SPIxCTRL_AUD contains the audio specific protocol control bits. When AUDEN = 1 the peripheral operates like an audio CODEC host or client. The audio protocol requires certain features of the SPI protocol and therefore overrides some SPI settings.

The peripheral uses the serial audio I8S protocol defined herein. In each of the modes available for the I8S the serial clock is free running and audio data is always transferred. For an example of AM824 data flow see the following figure.

Figure 50-21. Example of AM824 Data Flow Transmit/Receive

Four pins make up the serial interface. However, each audio connection is only half-duplex so SDO exists only on the transmit side and SDI exists only on the receive side of the interface. The four pins are:

  • SDI: Serial Data Input
  • SDO: Serial Data Output
  • SCK: Serial Clock
  • LRC: Left/Right Clock (on SS/FSYNC)

I8S allows multiple channels of data to be transmitted on a single data line. The I8S interface is similar to the 2 channel serial audio interface I2S with the exception that more channels are transmitted within a sample frame or sample period. Basically defined as an 8 channel TDM interface (left or right justified) with a 50% duty cycle LRC clock.

As with the I2S interface the I8S interface is comprised of two control clocks, a frame synchronization pulse (LRC), a serial clock (SCK), and the serial audio data line (SDO/SDI). Several Audio Modes can be selected, standard I8S, right justified, left justified, AM824 24, 20,16-bit (slot) Raw Audio, 32 bit data, 16-bit x2 packed, 24-bit x 4bit packed, 16, 20, 24-bit MSB aligned with lower bits muted (ie filled with ‘1 or ‘0 determined by user with DATFILL bit), and Host with multiple client transmit operation.

Each channel block is comprised of the audio data word (32, 24, 20, or 16). When specified the remainder of the 32bit word for 24, 20, 16 is padded with zeros or don’t cares depending on the type of Audio mode selected. In all modes the audio word is transmitted with the MSB first 2’s compliment format and the word size of 32 bits.

The function of the FSYNC pulse (LRC) is to identify the beginning of the frame and is indicated by the rising edge of the pulse and the frame rate is at the audio sample rate such as 48Khz. The FSYNC pulse (LRC) has two separate required representations:
  1. For the width to be equivalent to a channel block or,
  2. Where the width is equivalent to a single period of the serial clock which is more common with a TDM interface.

In TPD mode is recommended to not enable the devices dedicated as clients interrupts. The SPITUREN, SPIROUEN, and FRMERREN for the Clients should all be disabled and only enable the Host's interrupts as needed.

Channel Block Alignment with the FSYNC (LRC) Pulse

There are two options for the alignment of the first channel block with the rising or falling edge of the FSYNC (LRC): 1. the beginning of the channel block aligns with the rising edge of FSYNC (LRC) or 2. the beginning of the channel block aligns with the falling edge of FSYNC (LRC).

The purpose of the SCK is to send the audio data into and out of the serial audio ports. The frequency of the SCK is directly proportional to the system audio sample rate, the number of channel blocks in a frame and the bit-width of each channel block.

SCK operates at a maximum of 256*Auto sample rate. An Example with the sample rate at 48Khz:

  • 8 channel frame with 32 bit channel blocks at 48Khz requires a 12.2880 Mhz SCK