41.7.3 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.

Table 41-3. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTENCLR
Offset:	0x08
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
								DATARDY
Access								R/W
Reset								0

Bit 0 – DATARDY Data Ready Interrupt (TRNG) Enable

Writing a '1' to this bit will clear the Data Ready Interrupt (TRNG) Enable bit, which disables the corresponding interrupt request.

Writing a '0' to this bit has no effect. Reading this bit provides the following information.

Value	Description
0	The TRNG interrupt is disabled.
1	The TRNG interrupt is enabled.