41.7.5 Interrupt Flag Status and Clear
Note: Interrupt flags must be cleared and then read back to confirm the clear before
exiting the ISR to avoid double interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x0A |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATARDY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – DATARDY Data Ready Interrupt Flag
This flag is set when a new random value is generated, and the TRNG interrupt will be generated if this interrupt is enabled (INTENSET.DATARDY bit (INTENSET <0>) =1).
This flag is cleared by writing a '1' to the flag or by reading the DATA register.
Writing a '0' to this bit has no effect.