13.5.2 Initialization and Normal Operation
On reset, the cache controller data entries are all invalidated, and the cache is disabled. The cache is transparent to processor operations. The cache controller is activated through the use of its configuration registers. The configuration interface is memory mapped in the APB bus.
Follow these steps to enable the cache controller:
- Verify that the CMCC is disabled by reading the SR.CSTS value.
- Enable the CMCC by writing '1' in CTRL.CEN. The module is disabled by writing a '0' in CTRL.CEN.