16.13.1 Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRL |
| Offset: | 0x0000 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CMD[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMD[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | |||||||||
| Access | W | ||||||||
| Reset | 0 |
Bits 31:16 – CMD[15:0] Command Register
0x0 = No operation (NOOP)
0x1-0xA4FF = Reserved
0xA500 = 32-bit Cyclic Redundancy Code (CRC32)
0xA501 = Global Memory built-in self-test (MBIST)
0xA502 = Memory Set (MSET)
0xA503-0xFFFF = Reserved
Note: Invalid commands are reported into
STATUSA.PERR. Partial writes of the CMD bit field are ignored and reported in
STATUSA.PERR.
Bit 0 – SWRST Software Reset
Software reset has the highest priority. If this bit is set in a write all other bits are ignored.