16.13.9 Status B
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | STATUSB |
Offset: | 0x0104 |
Reset: | 0x00000000 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
HPE | DBGPRES | ||||||||
Access | R | R | |||||||
Reset | 0 | x |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DCCD1 | DCCD0 | BCCD1 | BCCD0 | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | x | x |
Bit 10 – HPE Hot-Plugging Enable
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the TCK/SWCLK function is changed. Only a power-reset or an external reset can set it again.
Bit 8 – DBGPRES Debugger Present
This bit is set when a debugger probe is detected.
Only a POR or external reset can reset this bit.
Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0]
This bit is set when DCCx register is written.
This bit is cleared when DCCx register is read.
Reset by APB reset.
Bits 0, 1 – BCCDx BOOT Communication Channel x Dirty [x=1..0]
This bit is set when BCCx register is written.
This bit is cleared when BCCx register is read.
Reset by APB reset and modified by the Boot ROM at boot time.